In the design, manufacture and assembly of semiconductor chips, there has been a well established convention that wire bond pads are placed in a single row at the periphery of the die or in the case of certain chips such as memory devices, in a row in the center of the chip. This is illustrated in FIG. 1. As bond pad counts increase and bond pad pitch becomes too small to reliably bond, changes in design for assembly has become necessary. To relieve some of the pressure caused by the demand for increasing numbers of input and output terminals (I/O), additional rows of peripheral contacts are becoming more common. This is illustrated in FIG. 2. Even so, the continuing reduction of design features on the IC chip continues to drive up I/O counts and thus this may prove to be of only temporary advantage and wire bonding lands may eventually need to be placed over active areas of silicon on the IC. Bonding locations are presently provided over active areas of silicon today for flip chip devices FIG. 3 provides an illustration of examples of area array flip chip bump configurations, however these terminations are not subjected to the rigors of wire bonding.
While flip chip provides the advantage to make connections over active areas of the IC, wire bonding remains a highly desirable method for interconnection due to its greater manufacturing infrastructure and greater versatility. At the present, however, there is a general prohibition against placing wire bonding I/O terminals over active areas of the chip even though it offers a direct connection rather than routing various power ground and signal interconnections to the edge of the chip. In the present situation, however, there are practical reasons for this prohibition based on the fact that the wire bonding process, as currently practiced, will likely damage any active circuitry beneath the bond pad.
Still, there remain significant advantages to making interconnections within the active area of the chip for cost, performance and ease of assembly reasons. It is for these reasons, among others, that flip chip technology was developed. While flip chip technology offers definite advantages in terms of the number of I/O that can be connected and makes available a coarser pitch for I/O terminals, the assembly process can be challenging and reliability issues are an increasing concern due to the mismatch in CTE. Thus, at present, most chip assembly still relies on established wire bonding methods.
Concurrently, with the desire to take advantage of the prospective gains and make reliable wire bonds over active areas of the chip that do not damage the circuitry beneath the contacts, there is a growing need for new methods of wire bonding that do not damage the brittle, low dielectric constant or so-called Low K dielectrics used in advanced IC manufacture. Thus, it would thus be doubly advantageous to allow wire bond pads to be placed any where on the chip to free up area on the surface of the IC.
While attractive conceptually and the object of some earlier experimentation, the potential advantages of wire bonding, over active areas of the chip remains an elusive goal and, to date, so far as is know, a reliable method has, as of yet, been unrealized in production. Also as noted earlier even with peripherally leaded structures, with ever smaller I/O terminals being used and the newer more brittle and easily damaged low dielectric constant insulation materials, the deformation and damage of the subsurface of the IC chip structure is an ever present risk and concern. Thus there exists a need and opportunity to better define structures and methods that will allow the user to make wire connections over active areas of the chip and improve the performance and yield of chip packaging.